xilinx公司的XC3S1000的芯片后面还有一串字母和数字代表什么意思?希望能有个详细的说明.

xilinx FPGA 在调用ip核时,顶层模块调用后综合成功,但是implement时,map出问题总,怎么解决
ERROR:Place:1206 - This design contains a global buffer instance,
,driving the net,,that is driving the
following (first 30) non-clock source pins off chip.
< PIN:CLKOUT.O; >
This design practice,in Spartan-6,can lead to an unroutable situation due
to limitations in the global routing.If the design does route there may be
excessive delay or skew on this net.It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1.If you wish to override this recommendation,you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.Although the net
may still not route,you will be able to analyze the failure in FPGA_Editor.
< PIN "CLK75MhZ/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1136 - This design contains a global buffer instance,
,driving the net,,that is driving the
following (first 30) non-clock source pins.
< PIN:CLKOUT.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay,skew or unroutable
situations.It is recommended to only use a BUFG resource to drive clock
loads.If you wish to override this recommendation,you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "CLK75MhZ/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

用XILINX FPGA芯片XC5VLX155设计了块PCB,将芯片焊接上后,未上电直接测试1V与GND之间的电阻只有6.5欧姆,有经验的人说这是正常的,他遇到过XILINX芯片的电源与地之间的电阻只有4欧姆的情况,也是正常的,请问是这样吗,现在不确定是否是将1V电源与地短路,所以不敢上电测试,给XILINX技术支持打电话还要什么Webcase,远水解不了近渴,高手在民间,还请高手指导,

请问xilinx里面的dds的ip核的phase increment (PINC)和phase offset ,看datasheet里面是调节频率和相位的,事实是不是这样?还有我见过一个bufg函数,到底是怎么用的.

xilinx FPGA 综合 布局布线都是干了什么事情啊?
综合 synthesize
执行 implement 包括 translate,map,place&route
仿真又分这四种 -behavioural,post-translate,post-map,post-route
1.为社么第一个behavioural不像其他的那样叫post-synthesize呢?
2.以上的每个英文单词,执行的时候都是干了什么事情啊?
3.那4个仿真,跟网上说的前仿真后仿真（功能仿真,布线后仿真等等）有什么对应关系?这些个英文准确的中文专业翻译应该怎么说?
4.时序约束,除了调整上升沿下降沿时间还有啥用?貌似我只用过管脚约束没用过时序约束,