这是我自己写的，应该能满足你的要求！
顶层实体
--topo.vhd
--
--
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY top IS
PORT(
CLK1Hz :IN STD_LOGIC;
SET :IN STD_LOGIC;
NODE :IN STD_LOGIC;
LED1 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED2 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED3 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED4 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED5 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
LED6 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END top;
ARCHITECTURE rtl of top IS
COMPONENT adjuster
PORT(
CLK1Hz :IN STD_LOGIC;
SET :IN STD_LOGIC;
NODE :IN STD_LOGIC;
EN :IN STD_LOGIC;
S_ENOUT :IN STD_LOGIC;
M_ENOUT :IN STD_LOGIC;
CLK :OUT STD_LOGIC;
S_CE :OUT STD_LOGIC;
M_CE :OUT STD_LOGIC;
H_CE :OUT STD_LOGIC
);
END COMPONENT;
COMPONENT counter60
PORT(
CLK1Hz :IN STD_LOGIC;
EN :IN STD_LOGIC;
ENOUT :OUT STD_LOGIC;
LOW :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT counter24
PORT(
in_date :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out_date :OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END COMPONENT;
COMPONENT display
PORT(
CLK1Hz :IN STD_LOGIC;
EN :IN STD_LOGIC;
ENOUT :OUT STD_LOGIC;
LOW :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
CONSTANT VCC :STD_LOGIC :="1";
SIGNAL VCC_CON :STD_LOGIC;
SIGNAL S_ENOUT :STD_LOGIC;
SIGNAL M_ENOUT :STD_LOGIC;
SIGNAL CLK :STD_LOGIC;
SIGNAL S_CE :STD_LOGIC;
SIGNAL M_CE :STD_LOGIC;
SIGNAL H_CE :STD_LOGIC;
SIGNAL SL :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL SH :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ML :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL MH :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HL :STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL HH :STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
ADJUST_CONTROL :adjuster
PORT MAP(
CLK1Hz =>CLK1Hz,
SET =>SET,
MODE =>MODE,
EN =>VCC_COM,
S_ENOUT=>S_ENOUT,
M_ENOUT=>M_ENOUT,
CLK =>CLK,
S_CE =>S_CE,
M_CE =>M_CE,
H_CE =>H_CE
);
VCC_CON <= VCC;
SEC_CONTROL:counter60
PORT MAP(
CLK1Hz =>CLK,
EN =>S_CE,
ENOUT =>S_ENOUT,
LOW =>SL,
HIGH =>SH
);
MIN_CONTROL :counter60
PORT MAP(
CLK1Hz =>CLK,
EN =>M_CE,
ENOUT =>M_ENOUT,
LOW =>ML,
HIGH =>MH
);
HOUR_CONTROL :counter24
PORT MAP(
CLK1Hz =>CLK,
EN =>H_CE,
LOW =>HL,
HIGH =>HH
);
DIS_LED1 :display
PORT MAP(
in_date =>SL,
out_date =>LED1
);
DIS_LED2 :display
PORT MAP(
in_date =>SH,
out_date =>LED2
);
DIS_LED3 :display
PORT MAP(
in_date =>ML,
out_date =>LED3
);
DIS_LED4 :display
PORT MAP(
in_date =>MH,
out_date =>LED4
);
DIS_LED5 :display
PORT MAP(
in_date =>HL,
out_date =>LED5
);
DIS_LED6 :display
PORT MAP(
in_date =>HH,
out_date =>LED6
);
END rtl;
60进制计数模块
--counter60.vhd
--
--
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counter60 IS
PORT(
CLK1Hz :IN STD_LOGIC;
EN :IN STD_LOGIC;
ENOUT :OUT STD_LOGIC;
LOW :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END counter60;
ARCHITECTURE rtl of counter60 IS
signal LOW_reg :std_logic_vector(3 DOWNTO 0) :="0000";
signal HIGH_reg :std_logic_vector(3 DOWNTO 0) :="0000";
BEGIN
LOW_PROC :PROCESS(CLK1HZ,EN)
BEGIN
IF rising_edge(CLK1HZ) THEN
IF EN="1" THEN
IF LOW_REG="1001" THEN
LOW_REG<="0000";
ELSE
LOW_REG<=LOW_REG + "1";
END IF;
END IF;
END IF;
END PROCESS;
LOW<=LOW_REG;
HIGH_PROC :PROCESS(CLK1HZ,EN)
BEGIN
IF rising_edge(CLK1HZ) THEN
IF EN="1" THEN
IF LOW_REG="1001" THEN
IF HIGH_REG="0101" THEN
HIGH_REG<="0000";
ELSE
HIGH_REG<=HIGH_REG + "1";
ENF IF;
END IF;
END IF;
END IF;
END PROCESS;
high<=high_reg;
enout<="1" when LOW_REG="1001" AND HIGH_REG="0101" ELSE "0";
END rtl;
24进制BCD码计数模块
--counter24.vhd
--
--
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY counter24 IS
PORT(
CLK1Hz :IN STD_LOGIC;
EN :IN STD_LOGIC;
ENOUT :OUT STD_LOGIC;
LOW :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
HIGH :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END counter24;
ARCHITECTURE rtl of counter24 IS
signal LOW_reg :std_logic_vector(3 DOWNTO 0) :="0000";
signal HIGH_reg :std_logic_vector(3 DOWNTO 0) :="0000";
signal CLR :std_logic :="0";
BEGIN
LOW_PROC :PROCESS(CLK1HZ,EN,CLR)
BEGIN
IF rising_edge(CLK1HZ) THEN
IF EN="1" THEN
IF LOW_REG="1001" OR CLR="1" THEN
LOW_REG<="0000";
ELSE
LOW_REG<=LOW_REG + "1";
END IF;
END IF;
END IF;
END PROCESS;
LOW<=LOW_REG;
HIGH_PROC :PROCESS(CLK1HZ,EN)
BEGIN
IF rising_edge(CLK1HZ) THEN
IF EN="1" THEN
IF CLR="1" THEN
HIGH_REG<="0000";
ELSEIF LOW_REG="1001" THEN
HIGH_REG<=HIGH_REG + "1";
END IF;
END IF;
END IF;
END PROCESS;
HIGH<=HIGH_REG;
CLR<="1" WHEN LOW_REG="0011" AND HIGH_REG="0010" ELSE "0";
END rtl;
校正模块
--adjuster.vhd
--
--
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY adjuster IS
PORT(
CLK1Hz :IN STD_LOGIC;
SET :IN STD_LOGIC;
NODE :IN STD_LOGIC;
EN :IN STD_LOGIC;
S_ENOUT :IN STD_LOGIC;
M_ENOUT :IN STD_LOGIC;
CLK :OUT STD_LOGIC;
S_CE :OUT STD_LOGIC;
M_CE :OUT STD_LOGIC;
H_CE :OUT STD_LOGIC
);
END adjuster;
ARCHITECTURE rtl of adjuster IS
SIGNAL SEL :STD_LOGIC;
SIGNAL SCE_REG :STD_LOGIC;
SIGNAL MCE_REG :STD_LOGIC;
SIGNAL HCE)REG :STD_LOGIC;
SIGNAL CON :INTEGER RANGE 0 TO 3 := 0;
BEGIN
COUT:PROCESS(MODE,SET)
BEGIN
IF rising_edg(MODE) THEN
IF CON = 3 RHEN
CON<=0;
ELSE
CON<=CON +1;
END IF;
END IF;
END PROCESS;
CON_PRO:PROCESS(CON)
BEGIN
CASE CON IS
WHEN 0=>SEL<="1";
SCE_REG<="0";
MCE_REG<="0";
HCE_REG<="0";
WHEN 1=>SEL<="0";
SCE_REG<="1";
MCE_REG<="0";
HCE_REG<="0";
WHEN 2=>SEL<="0";
SCE_REG<="0";
MCE_REG<="1";
HCE_REG<="0";
WHEN 3=>SEL<="0";
SCE_REG<="0";
MCE_REG<="0";
HCE_REG<="1";
WHEN OTHERS =>SEL<="0";
SCE_REG<="0";
MCE_REG<="0";
HCE_REG<="0";
END CASE;
END PROCESS;
SEL_PRO:PROCESS(SEL)
BEGIN
CASE SEL IS
WHEN 0=>S_CE<=SCE_REG;
M_CE<=MCE_REG;
H_CE<=HCE_REG";
CLK<=SET;
WHEN 0=>S_CE<=EN;
M_CE<=S_ENOUT;
H_CE<=M_ENOUT";
CLK<=CLK1HZ;
WHEN OTHERS =>S_CE<=EN;
M_CE<=S_ENOUT;
H_CE<=M_ENOUT";
CLK<=CLK1HZ;
END CASE;
END PROCESS;
END rtl;
显示模块
--display.vhd
--
--
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY display IS
PROT(
in_date :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out_date :OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END display;
ARCHITECTURE rtl of display IS
BEGIN
CASE in_dateIS
WHEN "0000"=>out_date<="0111111";
WHEN "0001"=>out_date<="0000110";
WHEN "0010"=>out_date<="1011011";
WHEN "0011"=>out_date<="1001111";
WHEN "0100"=>out_date<="1100110";
WHEN "0101"=>out_date<="1101101";
WHEN "0110"=>out_date<="1111100";
WHEN "0111"=>out_date<="0000111";
WHEN "1000"=>out_date<="1111111";
WHEN "1001"=>out_date<="1100111";
WHEN OTHERS =>out_date<="0000000";
END CASE;
END PROCESS;
END rtl;
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